Register Transfer Level Model Research Articles

Incremental Concolic Testing of Register-Transfer Level Designs

Concolic testing is a scalable solution for automated generation of directed tests for validation of hardware designs. Unfortunately, concolic testing fails to cover complex corner cases such as hard-to-activate branches. In this paper, we propose an incremental concolic testing technique to cover hard-to-activate branches in register-transfer level (RTL) models. We show that a complex branch condition can be viewed as a sequence of easy-to-activate events. We map the branch coverage problem to the coverage of a sequence of events. We propose an efficient algorithm to cover the sequence of events using concolic testing. Specifically, the test generated to activate the current event is used as the starting point to activate the next event in the sequence. Experimental results demonstrate that our approach can be used to generate directed tests to cover complex corner cases in RTL models while state-of-the-art methods fail to activate them.

An FPGA Architecture for the RRT Algorithm Based on Membrane Computing

This paper investigates an FPGA architecture whose primary function is to accelerate parallel computations involved in the rapid-exploring random tree (RRT) algorithm. The RRT algorithm is inherently serial, while in each computing step there are many computations that can be executed simultaneously. Nevertheless, how to carry out these parallel computations on an FPGA so that a high degree of acceleration can be realized is the key issue. Membrane computing is a parallel computing paradigm inspired from the structures and functions of eukaryotic cells. As a newly proposed membrane computing model, the generalized numerical P system (GNPS) is intrinsically parallel; so, it is a good candidate for modeling parallel computations in the RRT algorithm. Open problems for the FPGA implementation of the RRT algorithm and GNPS include: (1) whether it possible to model the RRT with GNPS; (2) if yes, how to design such an FPGA architecture to achieve a better speedup; and (3) instead of implementing GNPSs with a fixed-point-number format, how to devise a GNPS FPGA architecture working with a floating-point-number format. In this paper, we modeled the RRT with a GNPS at first, showing that it is feasible to model the RRT with a GNPS. An FPGA architecture was fabricated according to the GNPS-modeled RRT. In this architecture, computations, which can be executed in parallel, are accommodated in different inner membranes of the GNPS. These membranes are designed as Verilog modules in the register transfer level model. All the computations within a membrane are triggered by the same clock impulse to implement parallel computing. The proposed architecture is validated by implementing it on the Xilinx VC707 FPGA evaluation board. Compared with the software simulation of the GNPS-modeled RRT, the FPGA architecture achieves a speedup of a 104 order of magnitude. Although this speedup is obtained on a small map, it reveals that this architecture promises to accelerate the RRT algorithm to a higher level compared with the previously reported architectures.

Automatic correction of RTL designs using a lightweight partial high level synthesis

Correction of the digital designs have emerged as a major bottleneck at Register Transfer Level (RTL) due to the growing complexity of the digital systems and shortening time-to-market. Existing automated correction methods face problems like large number of error root causes, poor scalability, and multiple design errors. To address these problems, we propose an automatic correction methodology based on a lightweight partial high level synthesis (HLS) flow which takes as inputs a golden C specification and a buggy RTL design and outputs the corrected RTL model. Synthesizing the specification using a HLS tool without considering the buggy RTL to obtain the corrected RTL is not the case because manual RTL optimizations done by the designer should be preserved so that the architecture of the corrected RTL design should be as similar as possible to that of the buggy one. The results on industrial large designs show that the proposed methodology achieves 92.3% less new resources and 81.1% less connections compared to synthesizing the golden specification using a HLS tool without considering the architecture of the buggy RTL design.

Automated Generation of Security Assertions for RTL Models

System-on-Chip (SoC) security is vital in designing trustworthy systems. Detecting and fixing a vulnerability in the early stages is easier and cost-effective. Assertion-based verification is widely used for functional validation of Register-Transfer Level (RTL) designs. Assertions can improve the controllability and observability that can lead to faster error detection and localization. Although assertions are widely used for functional validation of RTL models, there is limited effort in applying assertions to detect SoC security vulnerabilities. Specifically, a fundamental challenge in SoC security and trust validation is how to develop high-quality security assertions. In this article, we perform automated vulnerability analysis of RTL models to generate security assertions for six classes of vulnerabilities. Experimental results show that the generated security assertions can detect a wide variety of vulnerabilities. Our automated framework can drastically reduce the overall security validation effort compared to the manual development of security assertions. Automated generation of security assertions will enable assertion-based verification to be one of the most promising pre-silicon security sign-off solutions.

Analysis of the Digital System Simulation Levels for its Design Debugging

A brief analysis of the digital system design debugging is given, typical errors and inaccuracies of digital system designs at the development stage are listed. The levels of digital system design simulation are considered: simulation models at the level of queuing; register transfer level models; architecture and microarchitecture level models; quasi-timing logic diagram level models; models taking into account the spread of block delays. For each level of simulation, estimates of complexity and time costs are given, as well as the types of detected design errors.

CIMulator: A Computing in Memory Emulator Framework

In this brief, we present <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CIMulator</monospace> , an open-source, extensible modeling, simulation, and emulation framework for on-chip digital Computing-In-Memory (CIM) design and assessment. Featuring a synthesizable Register Transfer Level (RTL) model, <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CIMulator</monospace> encapsulates the fundamental in-memory bitline logic and the near-memory compute functionalities altogether. In this way, <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CIMulator</monospace> ensures cycle-accurate RTL simulation, as well as system-level processor/CIM integration and emulation on COTS (commercially off-the-shelf) FPGA devices with an end-to-end correctness guarantee. In addition, we adopt a CIM intrinsics programming approach and an instruction-level energy model to estimate the application program execution energy. We implement an illustrative CIM system design emulated on a Cyclone-IV FPGA device and assess the functionality and performances of several applications, demonstrating the effectiveness of the proposed methodology. The source code is available at <uri xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">https://github.com/adervay1/CIMulator</uri> .

Early RTL delay prediction using neural networks

Nowadays, the digital chip design flow starts with formal specifications, which are mapped to Register Transfer Level (RTL) models using different underlying (micro-) architectures. By doing so, a hardware designer predicts and resolves time-critical parts to achieve an RTL-design that meets all constraints after synthesis. However, wrong predictions can be detected only later in the design flow, thus leading to long design iterations. Classical methods estimating delay in early design stages are constrained to the type of components or are computationally expensive for larger designs. This paper proposes a machine learning-based approach to estimate pin-to-pin delays for RTL combinational circuits. To improve the quality of the predictions we combine slew and delay estimation. To that end, training data are built using features of components generated by a model-driven hardware generator framework. Ground truth labels for delays, slews, and their interdependencies are extracted using open-source tools for logic synthesis and static timing analysis. Two different datasets are built: one targeting logic gates and multiplexers and an enlarged one, which generalizes to more RTL primitives A model trained using the former dataset achieves, on average, a coefficient of determination R2 of 87% when evaluating over 4-bit prefix adders. Using the enlarged dataset, the best model reaches an R2 of 77%. On average, our models are 8.4× faster w.r.t the time required to run synthesis and timing analysis. Results show that generalizing to more primitives decreases the models’ performance, but the runtime benefit is maintained. Based on the delay estimation, critical areas of the design can be detected and proper microarchitecture decisions can be taken earlier and faster in the design flow.

A Hybrid Method for Equivalence Checking Between System Level and RTL

Deep State Sequence-based (DSS) equivalence checking and path-based equivalence checking have been successfully applied for verification of digital designs between System Level Model (SLM) and Register Transfer Level (RTL). The DSS-based equivalence checking method can validate designs without mapping information, but the query size for each DSS is large compared with path-based verification. The query size for path-based methods is small, but the number of comparisons is large. In this work, we combine the advantages of DSS-based methods and path-based methods. We use DSS-based methods to find the corresponding paths and use cut-points like in path-based methods to split the DSS to reduce the query size. Finite State Machine with Datapath (FSMD) is used to represent the SLM and RTL models. Experimental results demonstrate that our method can effectively validate the designs and reduce the query size for DSS-based equivalence checking method.

RTL Conversion Method From Pipelined Synchronous RTL Models Into Asynchronous Ones

In this paper, we propose a conversion method from pipelined synchronous Register Transfer Level (RTL) models into pipelined asynchronous RTL models with bundled-data implementation. To know data-path resources controlled by each pipeline stage, the proposed method generates a control data flow graph (CDFG) from synchronous RTL models. After generating the CDFG, the proposed method generates asynchronous RTL models by analyzing each pipeline stage on the CDFG, assigning asynchronous control modules, and connecting the control modules to the data-path resources. In addition, we also propose optimization methods during the conversion. In the experiment, we converted four pipelined synchronous RTL models into pipelined asynchronous ones. In addition, we performed logic synthesis for the converted asynchronous RTL models to check the quality of the asynchronous RTL models. The synthesized asynchronous circuits without the optimization methods could reduce the energy consumption by 1.47&#x0025; on average compared to synchronous circuits. Moreover, the optimization methods could reduce the energy consumption by 15.12&#x0025; on average compared to synchronous circuits. Furthermore, the optimization methods reduced the energy consumption by up to 34.72&#x0025; compared to asynchronous circuits without the optimization methods.

Simplified introduction of power intent into a register-transfer level model

Simplified introduction of power intent into a register-transfer level model

Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions

Today's systems on chip (SoCs) require a complex design and verification process. In early design stages, high-level debugging of the SoC functionality is feasible on TLM (Transaction-Level Modeling) descriptions. To ease debugging of such SoC's models, Assertion-Based Verification (ABV) enables the runtime verification of temporal properties. In the last design stages, RTL (Register Transfer Level) descriptions of hardware blocks expose microarchitectural details. To gain confidence in the validity of system level properties after this TLM-to-RTL synthesis, transaction level assertions must be reverifiable on RTL models. To address that issue, we propose refinement rules for the automatic system level to signal level transformation of PSL assertions (Property Specification Language, IEEE standard 1850). We sketch the architecture of a prototype tool that automates this refinement, and we give some illustrative examples for a realistic use case.

Scalable Concolic Testing of RTL Models

Simulation is widely used for validation of Register-Transfer-Level (RTL) models. While simulating with millions of random or constrained-random tests can cover majority of the functional scenarios, the number of remaining scenarios can still be huge (hundreds or thousands) in case of today's industrial designs. Hard-to-activate branches are one of the major contributors for such remaining/untested scenarios. While directed test generation techniques using formal methods are promising in activating branches, it is infeasible to apply them on large designs due to state space explosion. In this article, we propose a fully automated and scalable approach to cover the hard-to-activate branches using concolic testing of RTL models. While application of concolic testing on hardware designs has shown some promising results in improving the overall coverage, they are not designed to activate specific targets such as uncovered corner cases and rare scenarios. In other words, existing concolic testing approaches address state space explosion problem but leads to path explosion problem while searching for the uncovered targets. Our proposed approach maps directed test generation problem to target search problem while avoiding overlapping searches involving multiple targets. This article makes two important contributions. (1) We propose a directed test generation technique to activate a target by effective utilization of concolic testing on RTL models. (2) We develop efficient learning and clustering techniques to minimize the overlapping searches across targets to drastically reduce the overall test generation effort. Experimental results demonstrate that our approach significantly outperforms the state-of-the-art methods in terms of test generation time (up to 205X, 69X on average) as well as memory requirements (up to 31X, 7X on average).

DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase

Dealing with resource constraints is an inevitable feature of embedded systems. Power and performance are the main concerns beside others. Pre-silicon analysis of power and performance in today’s complex embedded designs is a big challenge. Although RTL (Register-Transfer Level) models are more precise and reliable, system-level modeling enables the power and performance analysis of complex and dense designs in the early design phase. Virtual prototypes of systems prepared through architectural simulation provide a means of evaluating non-existing systems with more flexibility and minimum cost. Efficient interplay between power and performance is a key feature within virtual platforms. This article focuses on dynamic voltage and frequency scaling (DVFS), which is a well-known system-level low-power design technique together with its more efficient implementations modeled through architectural simulation. With advent of new computing paradigms and modern application domains with strict resource demands, DVFS and its efficient hardware-managed solutions get even more highlighted. This is mainly because they can react faster to resource demands and thus reduce induced overhead. To that end, they entail an effective collaboration between software and hardware. A case review in the end wraps up the discussed topics.

Formal Equivalence Checking Between System-Level and RTL Descriptions without Pre-Given Mapping Information

The growing complexity of digital designs makes it harder to discover inconsistency between system-level model (SLM) and register transfer-level (RTL) model. Equivalence checking is a promising solution to verify that the RTL description meets the requirements of the corresponding SLM description. However, the previously proposed formal equivalence checking approaches cannot handle designs if the mapping information is not given beforehand. Deep state sequences (DSSs)-based equivalence checking approach is the state-of-the-art equivalence checking approach based on Finite State Machines with Data Paths (FSMDs). But previously proposed DSS-based equivalence checking approach compared all the path-pairs blindly without pre-given mapping information, which wasted most verification efforts on useless comparisons. This paper proposes a novel DSS-based equivalence checking approach which can handle designs without pre-given mapping information and improve verification efficiency. Simulation technique is first used in our approach to generate mapping information of paths between SLM and RTL. With the generated mapping information, our approach can handle designs without pre-given mapping information. Only the generated corresponding path-pairs need to be compared by symbolic simulation, which improves the verification efficiency without blind comparisons. The experimental results show that the proposed approach can handle designs without pre-given mapping information and improve the efficiency of equivalence checking.

Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models

Only few solutions for Hardware Trojan (HT) detection work at Register-Transfer Level (RTL), thus delaying the identification of possible security issues at lower abstraction levels of the design process. In addition, the most of existing approaches work only for specific kinds of HTs. To overcome these limitations, we present a verification approach that detects different types of HTs in RTL models by exploiting an efficient control-flow subgraph matching algorithm. The prototypes of HTs that can be detected are modelled in a library by using Control-Flow Graphs (CFGs) that can be parametrised and extended to cover several variants of Trojan patterns. Experimental results show that our approach is effective and efficient in comparison with other state-of-the-art solutions.

A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

The emergence of power as a first-class design constraint has fueled the proposal of a growing number of optimization techniques, seeking the best tradeoff to reach the maximum energy efficiency. Effective adaptation strategies depend critically on the monitoring method as an incorrect assessment of the system’s state will result in poor decision making. Yet it is indeed a fundamental issue: how to get a precise estimation of the system’s state, and especially in a cost-effective way? We address this question for the self-observation of the power consumption. We develop a method that combines several data mining algorithms to monitor the toggling activity on a few relevant signals selected at the register transfer-level. Our approach is based on a generic flow that is able to produce a power model for any register transfer level (RTL) circuit on any technology. This contribution is evaluated on a system on chip RTL model implemented on an field-programmable gate array technology. The experiments demonstrate that the proposed method achieves the accuracy of analog power sensors (error lower than 1%) at a finer granularity and in a cost-effective way.

基于事务数据流的可重构SoC性能分析方法研究与实现

粗粒度可重构体系结构由于其配置速度快、计算加速比高、适应性好、低功耗特性等优点已成为高性能可重构SoC协处理器的重要解决方案。可重构SoC的性能分析，普遍使用传统的寄存器传输级代码仿真分析方法，存在使用不方便、分析效率较低等不足之处。本文提出一种基于事务数据流图的可重构SoC性能分析方法，该方法结合应用程序数据流图与体系结构特征，构建可重构协处理器的事务数据流图并标注图节点功能属性相应的硬件性能参数；然后采用基于层次搜索的广度优先性能搜索算法，通过分析类树形结构的事务数据流图，得到可重构协处理器运行应用程序的性能分析结果。实验表明所提出的方法可以较为准确高效的分析可重构SoC体系结构应用计算性能，有助于可重构SoC早期体系结构设计和设计空间探索。 Coarse grained reconfigurable architecture has become an important solution for high performance re-configurable SoC coprocessor because of its high configuration speed, fast calculation speed, good adaptability and low power consumption. However, the traditional performance analysis method of register transfer level modeling is still widely used. To overcome the shortage of traditional performance analysis in flexibility and efficiency, we propose a new method for reconfigurable SoC performance analysis based on transaction data flow graph. This method combined application data flow graph with architectural characteristics through constructing the transaction dataflow graph of reconfigurable coprocessor and labeling hardware performance parameters corresponding to functional properties. Using the breadth first search algorithm based on hierarchical search to analyze the tree-like transaction dataflow graph, we can get the performance of reconfigurable coprocessor running applications. The result of the experiment indicates that the proposed method calculates the structure of the reconfigurable SoC quite accurately, and benefits the design of architecture and design space exploration.

A proposed synthesis method for Application-Specific Instruction Set Processors

Due to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a commonly used technique, but the automated hardware model generation is less frequently applied in terms of final RTL implementations. Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms of resource requirement and operation frequency. The design framework implementing the algorithms required by the synthesis method is also presented.

Investigating SystemAda

VHDL as a hardware description language has some short-comings for system level modeling. Since previous researches [10] tried to extend this language for high level modeling, using Ada structures, and also it has derived some of its basic structures from Ada at first, we have decided to extend Ada to a form called SystemAda that can model hardware at transaction level modeling. Ada because of its intrinsic features like concurrency and object orientation can be a good candidate for a high level hardware modeling language. In our previous works we have proved that Ada can have a link to Register Transfer Level (RTL) and Transaction Level Modeling (TLM) modeling [3]. Here we have proofed the detailed characteristics of our TLM_FIFO channel -- just like the real TLM_FIFO -- and a way to TLM2.0 interfaces. Finally by simulation time comparison between SystemAda and SystemC TLM equivalent models we have proved that there is no simulation time penalty in SystemAda over SystemC.

A Novel Simulation Fault Injection using Electronic Systems Level Simulation Models

Abstract—In this paper, we propose a novel simulation fault injection method for the dependability analysis of complex SoCs using 32 nm technology. In previous simulation fault injections, the original simulation model is modified to implement a saboteur module or many mutants. This creates a problem since the architectural complexity of current SoCs is expected to increase rapidly in the 32 nm era. Furthermore, the modification process may incur additional tasks, such as verification and validation of the modified simulation model. Our simulation fault injection environment uses the modified SystemC simulation kernel augmented for fault injection experiments. The proposed methodology offers the following advantages over previous simulation fault injection methods. First, it does not require changes in the target simulation design model. Second, it minimizes the simulation hardware resource requirements and simulation time. Third, it allows mixed simulation of the ESL model and the register transfer level model using wrappers. To demonstrate the effectiveness of the proposed methodology, we designed the SystemC models of MIPS and TMR MIPS processors and ran the benchmark SW from MiBench to compare the failure rates of the two processors.